SoC Architect in Neuenburg

Job Title: SoC Architect

Location: Switzerland

Job Type: Full time – Permanent

Salary: DOE

Role Overview:

This is an ASIC SoC Architect role – not an RF Architecture role.

Requiring strong understanding of embedded software, memory, security, test, analog/RF interfaces, and manufacturing.

Key Responsibilities:

• Own the digital SoC architecture: processor, interconnect, memory hierarchy, clock/reset, power domains and modes, peripherals, security, debug, test, and hardware/software partitioning
• Translate product requirements into architecture specifications, interfaces, verification objectives, and measurable power, performance, area, cost, and risk budgets
• Drive digital ASIC decisions covering IP selection and reuse, RTL architecture, low-power intent, CDC/RDC, DFT, implementation constraints, and design-for-verification
• Align Digital Design, Verification, IC Integration, software, validation, test, memory, analog/RF, CAD/PDK, package, and manufacturing contributors
• Lead architecture reviews and formal change control; support implementation, tape-out, silicon bring-up, qualification, yield improvement, and production issue resolution

Experience Required:

• Master’s degree in Electrical Engineering, Microelectronics, or a related field; Ph.D. preferred
• 12+ years in digital ASIC/SoC design, integration, or architecture, including substantial hands‑on RTL design using SystemVerilog or Verilog
• Proven ownership of a complex low-power SoC from architecture through tape-out, silicon bring-up, qualification, and production
• Deep knowledge of low-power digital design: clock and power gating, retention, isolation, voltage domains, memory optimization, wake‑up sequencing, always‑on logic, and UPF-based power intent
• Strong command of ASIC flows and trade‑offs, including synthesis, static timing analysis, CDC/RDC, DFT, verification, physical‑design constraints, and power/performance/area optimization
• Experience with reusable platforms, external IP qualification, embedded NVM/SRAM/OTP, secure boot, hardware security, and hardware/software partitioning
• Wireless‑connectivity integration knowledge is required. Automotive‑grade development, DFMEA/PFMEA, PPAP, formal change management, or medical‑customer requirements are advantages

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