DFT Engineer
Lausanne, Switzerland or UK
I’m working with an innovative semiconductor company developing high-speed, energy-efficient chip-to-chip connectivity solutions for next-generation electronic systems.
They are looking for an experienced DFT Engineer to join their growing engineering team, working across DFT implementation, test pattern development, timing, simulation and silicon bring-up.
This would suit someone who enjoys being hands‑on technically and wants to work on complex designs within a fast‑moving semiconductor environment.
Key Responsibilities
- Hierarchical MBIST and scan insertion, including scan compression
- Boundary Scan Design (BSD) implementation
- ATPG pattern generation, coverage analysis and driving towards high coverage metrics
- Running and debugging pattern simulations with timing
- Defining test‑mode timing constraints and analysing timing reports
- Supporting timing convergence across test modes
- Developing cycle‑accurate functional patterns using IJTAG methodologies
- Working closely with test and production engineering teams during probe and final test
- Supporting device bring‑up and debugging silicon issues
- Developing scripts and automation to improve DFT flows
What We’re Looking For
- 5+ years of experience in DFT
- Experience across DFT implementation, test pattern development and simulation
- Experience contributing to DFT solutions for complex ASIC or SoC designs
- Strong knowledge of IJTAG methodologies
- Experience with hierarchical MBIST insertion
- Experience with hierarchical scan insertion and scan compression
- Strong ATPG experience across different fault models
- Experience analysing fault coverage and driving coverage closure
- Strong debugging skills, particularly around timing‑aware pattern simulation
- Experience with industry‑standard EDA tools for DFT, timing and simulation
- Good scripting skills for automation
- Knowledge of SystemVerilog
Education
Bachelor’s degree or higher in Electronics, Electrical Engineering, Computer Engineering or a related discipline.
The Opportunity
You’ll be joining a company working at the forefront of high‑speed semiconductor connectivity, with the opportunity to contribute across the complete DFT lifecycle, from implementation and pattern generation through to silicon bring‑up and production test.
The role can be based in Lausanne, Switzerland or the UK.
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DFT Engineer in Lausanne Arbeitgeber: Intellectual Capital Resources Ltd
Intellectual Capital Resources Ltd ist ein hervorragender Arbeitgeber, der innovative Technologien im Bereich RF IC Design fördert. Mit einem starken Fokus auf Mitarbeiterentwicklung und einer kollaborativen Arbeitskultur bietet das Unternehmen zahlreiche Wachstumschancen in einem dynamischen Umfeld. Die Lage ermöglicht zudem den Zugang zu einem Netzwerk von Fachleuten und Ressourcen, die für die Entwicklung von mmWave- und SiGe-ICs entscheidend sind.
Kontaktdaten:
Intellectual Capital Resources Ltd Recruiting-Team
