ASIC Engineering Technical Leader in Thalwil

Cisco is seeking an ASIC Engineering Technical Leader to join our world-class Silicon One Analog Circuit Design team in Thalwil, Switzerland, pioneering industry-leading high-speed mixed-signal architectures that power the AI and cloud infrastructure era.

Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally.

Our innovations in silicon, optics, and hardware platforms are shaping the technology industry.

We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow.

Because full product development—from design to qualification to production is within our team, we’re able to think differently, experiment more, and work quickly.

Join us to power the future of the digital world.

Your Impact As an ASIC Engineering Technical Leader, you will define, design, and verify high-performance ASIC subsystems deployed across a range of Cisco platforms.

You will oversee the architecture and design of complex analog and mixed-signal circuits, driving innovative solutions and establishing robust verification strategies.

By collaborating with cross-functional teams, you will influence packaging and hardware requirements to ensure all power, performance, and area goals are met.

Your technical expertise will guide the development of reusable code methodologies, physical design functions, and advanced digital design flows, ultimately shaping the future of our high-volume ASIC releases.

Minimum Qualifications Masters + 8 years of related experience, or Ph D + 5 years of related experience, or equivalent related work experience Extensive experience in high-frequency CMOS circuit design and custom analog and mixed-signal circuit design.

Proficiency with the Cadence Virtuoso CAD design environment, including custom layout, DRC, LVS, and parasitic extraction.

Strong programming skills utilizing languages such as Skill, Verilog A, Tcl, Perl, Python, Matlab, or C.

Preferred Qualifications Experience in high-speed wireline Ser Des design, signal processing, and communication systems.

Familiarity with digital design flow (synthesis and P&R) and additional CAD tools (Siemens/Mentor, Synopsys).

Experience with coil design using EM field simulators (EMX, Momentum, HFSS) and knowledge of packaging technology.

Hands-on experience with measurement equipment and in-depth knowledge of version and project management tools (e. g., SOS, Jira).

A strong portfolio of publications and patents, with a proven ability to collaborate effectively within a multi-disciplined engineering team.

Why Cisco?

At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond.

We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds.

These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.

Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions.

Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless.

We work as a team, collaborating with empathy to make really big things happen on a global scale.

Because our solutions are everywhere, our impact is everywhere.

We are Cisco, and our power starts with you.

Cisco is an affirmative Action and Equal Opportunity Employer and all qualified applicants will receive consideration for employment without regard to race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or any other legally protected basis.

Cisco will consider for employment, on a case by case basis, qualified applicants with arrest and conviction records. #J-18808-Ljbffr